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A5 TP
05
0
TPA5050
SLOS492A - MAY 2006 - REVISED MAY 2006
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STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL
FEATURES
* * * * * * Digital Audio Formats: 16-24-bit I2S, Right-Justified, Left-Justified I2C Bus Controlled Single Serial Input Port Delay Time: 170 ms/ch at fs = 48 kHz Delay Resolution: One Sample Delay Memory Cleared on Power-Up or After Delay Changes - Eliminates Erroneous Data From Being Output 3.3 V Operation With 5 V Tolerant I/O and I2C Control Supports Audio Bit Clock Rates of 32 to 64 fs with fs = 32 kHz-192 kHz No external crystal or oscillator required - All Internal Clocks Generated From the Audio Clock Surface Mount 4mm x 4mm, 16-pin QFN Package
APPLICATIONS
* * * * High Definition TV Lip-Sync Delay Flat Panel TV Lip-Sync Delay Home Theater Rear-Channel Effects Wireless Speaker Front-Channel Synchronization
DESCRIPTION
The TPA5050 accepts a single serial audio input, buffers the data for a selectable period of time, and outputs the delayed audio data on a single serial output. One device allows delay of up to 170 ms/ch (fs = 48 kHz) to synchronize the audio stream to the video stream in systems with complex video processing algorithms. If more delay is needed, the devices can be connected in series.
* * *
*
SIMPLIFIED APPLICATION DIAGRAM
Audio Processor
SCLK TAS3103A or ATSC Processor BCLK LRCLK DATA
Digital Amplifier TAS5504A +TAS5122
3.3 V TPA5050
GND
VDD
BCLK LRCLK DATA
DATA_OUT
SCLK BCLK LRCLK DATA
3 I2C Delay Control
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
SDA SCL ADDx (2:0)
Copyright (c) 2006, Texas Instruments Incorporated
TPA5050
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SLOS492A - MAY 2006 - REVISED MAY 2006
PIN DESCRIPTIONS
RSA (QFN) PACKAGE (TOP VIEW)
DATA_OUT
BCLK
GND
14
16
LRCLK DATA SCL SDA
1
15
13
VDD
12
ADD2 ADD1 ADD0 GND
2
11
3
10
4
9
5
6
GND
GND
7
TERMINAL FUNCTIONS
TERMINAL NAME ADD0 ADD1 ADD2 BCLK DATA DATA_OUT GND LRCLK SCL SDA VDD Thermal Pad NO. 10 11 12 16 2 15 5-9, 14 1 3 4 13 I/O I I I I I O P I I I/O P I2C address select pin - LSB I2C address select pin I2C address select pin - MSB Audio data bit clock input for serial input. 5V tolerant input. Audio serial data input for serial input. 5V tolerant input. Delayed audio serial data output. Ground - All ground terminals must be tied to GND for proper operation Left and Right serial audio sampling rate clock (fs). 5V tolerant input. I2C communication bus clock input. 5V tolerant input. I2C communication bus data input. 5V tolerant input. Power supply interface. Connect to ground. Must be soldered down in all applications to properly secure device on the PCB. DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
DATA BCLK LRCLK DELAY MEMORY OUTPUT BUFFER
INPUT BUFFER
GND
GND
8
DATA_OUT
IC ADDx (2:0)
2
2 3
CONTROL
2
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)
VDD VI Supply voltage Input voltage DATA, LRCLK, BCLK, SCL, SDA ADD[2:0]
(1)
VALUE -0.3 to 3.6 -0.3 to 5.5 -0.3 to VDD+0.3 See Dissipation Rating Table -40 to 85 -40 to 125 -65 to 125 260
UNIT V V
Continuous total power dissipation TA TJ Tstg Operating free-air temperature range Operating junction temperature range Storage temperature range Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1)
C C C C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS (1)
PACKAGE RSA (1) TA 25C POWER RATING 2.5 W DERATING FACTOR 25mW/C TA = 70C POWER RATING 1.375 W TA = 85C POWER RATING 1.0 W
This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad.
RECOMMENDED OPERATING CONDITIONS
MIN VDD VIH VIL TA Supply voltage High-level input voltage Low-level input voltage VDD DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0] DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0] -40 3 2 0.8 85 MAX 3.6 UNIT V V V C
Operating free-air temperature
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DC CHARACTERISTICS
TA = 25C, VDD = 3 V (unless otherwise noted)
PARAMETER IDD IOH IOL IIH IIL Supply current Low-level output current High-level input current Low-level input current High-level output current DATA_OUT = 2.6 V DATA_OUT = 0.4 V DATA, LRCLK, BCLK, SCL, SDA, Vi = 5.5V, VDD = 3V ADD[2:0], Vi = 3.6V, VDD = 3.6V DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0], Vi = 0V, VDD = 3.6V TEST CONDITIONS VDD = 3.3 V, fs = 48 kHz, BCLK = 32 fs 7 7 MIN TYP 1.5 MAX 3 13 13 20 5 1 UNIT mA mA mA A A
TIMING CHARACTERISTICS (1) (2)
For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER fSCL tw(H) tw(L) tsu1 th1 t(buf) tsu2 th2 tsu3 (1) (2) Frequency, SCL Pulse duration, SCL high Pulse duration, SCL low Setup time, SDA to SCL Hold time, SCL to SDA Bus free time between stop and start condition Setup time, SCL to start condition Hold time, start condition to SCL Setup time, SCL to stop condition VPull-up = VDD A pull-up resistor 2 k is required for a 5 V I2C bus voltage.
tw(H) SCL tw(L)
TEST CONDITIONS No wait states
MIN 0.6 1.3 100 10 1.3 0.6 0.6 0.6
TYP
MAX 400
UNIT kHz s s ns ns s s s s
t su1 SDA
th1
Figure 1. SCL and SDA Timing
SCL th2 tsu2 SDA t(buf) tsu3
Start Condition
Stop Condition
Figure 2. Start and Stop Conditions Timing
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TPA5050
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Serial Audio Input Ports
over recommended operating conditions (unless otherwise noted)
PARAMETER fSCLKIN Frequency, BCLK 32 x fs, 48 x fs, 64 x fs tsu1 th1 tsu2 th2 Setup time, LRCLK to BCLK rising edge Hold time, LRCLK from BCLK rising edge Setup time, DATA to BCLK rising edge Hold time, DATA from BCLK rising edge LRCLK frequency BCLK duty cycle LRCLK duty cycle BCLK rising edges between LRCLK rising edges
BCLK (Input) th1 tsu1 LRCLK (Input) th2 tsu2 DATA
TEST CONDITIONS
MIN 1.024 10 10 10 10 32
TYP
MAX 12.288
UNIT MHz ns ns ns ns
48 50% 50%
192
kHz
LRCLK duty cycle = 50%
32
64
BCLK edges
Figure 3. Serial Data Interface Timing
APPLICATION INFORMATION AUDIO SERIAL INTERFACE
The audio serial interface for the TPA5050 consists of a 3-wire synchronous serial port. It includes LRCLK, BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the TPA5050 on the rising edge of BCLK. LRCLK is the serial audio left/right word clock. It is used to latch serial data into the internal registers of the serial audio interface. LRCLK is operated at the sampling frequency, fs. BCLK can be operated at 32 to 64 times the sampling frequency for right-justified, left-justified, and I2S formats. A system clock is not necessary for the operation of the TPA5050.
AUDIO DATA FORMATS AND TIMING
The TPA5050 supports industry-standard audio data formats, including right-justified, I2S, and left-justified. The data formats are shown in Figure 4. Data formats are selected using the I2C interface and register map (see Table 1).
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APPLICATION INFORMATION (continued)
(1) Right-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS LRCK L-Channel R-Channel
BCK (= 32 fS, 48 fS, or 64 fS) 16-Bit Right-Justified, BCK = 48 f S or 64 fS DATA 14 15 16 1 2 3 14 15 16 LSB 1 2 3 14 15 16 LSB
MSB 16-Bit Right-Justified, BCK = 32 f S DATA 14 15 16 1 2 3
MSB
14 15 16 LSB
1
2
3
14 15 16 LSB
MSB 18-Bit Right-Justified, BCK = 48 f S or 64 fS DATA 16 17 18 1 2 3
MSB
16 17 18 LSB
1
2
3
16 17 18 LSB
MSB 20-Bit Right-Justified, BCK = 48 f S or 64 fS DATA 18 19 20 1 2 3
MSB
18 19 20 LSB
1
2
3
18 19 20 LSB
MSB 24-Bit Right-Justified, BCK = 48 f S or 64 fS DATA 22 23 24 1 2 3
MSB
22 23 24 LSB
1
2
3
22 23 24 LSB
MSB
MSB
(2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH
1/fS LRCK L-Channel R-Channel
BCK (= 32 fS, 48 fS, or 64 fS)
DATA
1
2
3
N-2 N-1
N
1
2
3
N-2 N-1
N
1
2
MSB
LSB
MSB
LSB
(3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW
1/fS LRCK L-Channel R-Channel
BCK (= 32 fS, 48 fS, or 64 fS)
DATA
1
2
3
N-2 N-1
N
1
2
3
N-2 N-1
N
1
2
MSB
LSB
MSB
LSB
Figure 4. Audio Data Formats
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APPLICATION INFORMATION (continued) GENERAL I C OPERATION
The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 5. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The TPA5050 holds SDA low during acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. When the bus level is 5 V, pull-up resistors between 1 k and 2 k in value must be used.
8- Bit Data for Register (N) 8- Bit Data for Register (N+1)
2
Figure 5. Typical I2C Sequence There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 5. The 7-bit address for the TPA5050 is selectable using the 3 address pins (ADD2, ADD1, ADD0). Table 1 lists the 8 possible slave addresses. Table 1. I2C Slave Address
FIXED ADDRESS (4 MSB bits) 1101 1101 1101 1101 1101 1101 1101 1101 SELECTABLE ADDRESS BITS ADD2 0 0 0 0 1 1 1 1 ADD1 0 0 1 1 0 0 1 1 ADD0 0 1 0 1 0 1 0 1
SINGLE-AND MULTIPLE-BYTE TRANSFERS
The serial control interface supports both single-byte and multi-byte read/write operations for all registers. During multiple-byte read operations, the TPA5050 responds with data, a byte at a time, starting at the register assigned, as long as the master device continues to respond with acknowledges.
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The TPA5050 supports sequential I2C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I2C write transaction has taken place. For I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.
SINGLE-BYTE WRITE
As shown is Figure 6, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I2C device address and the read/write bit, the TPA5050 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the TPA5050 internal memory address being accessed. After receiving the register byte, the TPA5050 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TPA5050 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer.
Start Condition Acknowledge Acknowledge Acknowledge
A6
A5
A4
A3
A2
A1
A0
R/W ACK A7
A6
A5
A4
A3
A2
A1
A0 ACK D7
D6
D5
D4
D3
D2
D1
D0 ACK
I2C Device Address and Read/Write Bit
Register
Data Byte
Stop Condition
Figure 6. Single-Byte Write Transfer
MULTIPLE-BYTE WRITE AND INCREMENTAL MULTIPLE-BYTE WRITE
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the TPA5050 as shown in Figure 7. After receiving each data byte, the TPA5050 responds with an acknowledge bit.
Register
Figure 7. Multiple-Byte Write Transfer
SINGLE-BYTE READ
As shown in Figure 8, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be read. As a result, the read/write bit is set to a 0. After receiving the TPA5050 address and the read/write bit, the TPA5050 responds with an acknowledge bit. The master then sends the internal memory address byte, after which the TPA5050 issues an acknowledge bit. The master device transmits another start condition followed by the TPA5050 address and the read/write bit again. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA5050 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
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Start Condition
Repeat Start Condition Acknowledge Acknowledge Acknowledge
Not Acknowledge
A6
A5
A1
A0 R/W ACK A7
A6
A5
A4
A0 ACK
A6
A5
A1
A0 R/W ACK D7
D6
D1
D0 ACK
I2C Device Address and Read/Write Bit
Register
I2C Device Address and Read/Write Bit
Data Byte
Stop Condition
Figure 8. Single-Byte Read Transfer
MULTIPLE-BYTE READ
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TPA5050 to the master device as shown in Figure 9. With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte.
Start Condition Repeat Start Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge Not Acknowledge
A6
A0 R/W ACK A7
A6
A5
A0 ACK
A6
A0 R/W ACK D7
D0
ACK D7
D0 ACK D7
D0 ACK
I2C Device Address and Read/Write Bit
Register
I2C Device Address and Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop Condition
Figure 9. Multiple-Byte Read Transfer
TPA5050 Operation
The following sections describe the registers configurable via I2C commands for the TPA5050. Only a single decoupling capacitor (0.1 F-1 F) is required across VDD and GND. The ADDx terminals can be directly connected to VDD or GND. Table 1 describes the I2C addresses selectable via the ADDx terminals. A schematic implementation of the TPA5050 is shown in Figure 10.
3.3 V 0.1 mF
VDD Digital Audio Word Clock Bit Clock DATA LRCLK BCLK GND
DATA_OUT SDA SCL ADD0 ADD1 ADD2 GND
Delayed Audio I C Data I C Clock
2 2
I C Address Select
2
Figure 10. TPA5050 Schematic
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SERIAL CONTROL INTERFACE REGISTER SUMMARY
Table 2. Serial Control Register Summary
REGISTER 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 REGISTER NAME Control Register Right Delay Upper (5 bits) Right Delay Lower (8 bits) Left Delay Upper (5 bits) Left Delay Lower (8 bits) Frame Delay RJ Packet Length Complete Update NO. OF BYTES 1 1 1 1 1 1 1 1 CONTENTS Description shown in subsequent section Description shown in subsequent section Description shown in subsequent section Description shown in subsequent section Description shown in subsequent section Description shown in subsequent section Description shown in subsequent section Description shown in subsequent section INITIALIZATION VALUE 00 00 00 00 00 00 00 00
CONTROL REGISTER (0x01)
The control register allows the user to mute a specific audio channel. It is also used to specify the data type (I2S, Right-Justified, or Left-Justified. Table 3. Control Registers (0x01) (1)
D7 0 0 1 1 - - - - (1) D6 0 1 0 1 - - - - D5 X X X X X X X X D4 X X X X X X X X D3 X X X X X X X X D2 X X X X X X X X D1 - - - - 0 0 1 1 D0 - - - - 0 1 0 1 Left channel is MUTED. Right channel is MUTED. Left and Right channel are MUTED. I2S data format Right-justified data format (see PACKET LENGTH register 0x07) Left-justified data format Bypass mode - data is passed straight through without delay. FUNCTION Left and Right channel are active.
Default values are in bold.
AUDIO DELAY REGISTERS (0x02-0x05)
The audio delay for the left and right channels is fixed by writing a total of 13 bits (2 byte transfer) to upper and lower registers as specified in Table 1. A multiple byte transfer should be performed starting with the control register and following with 4 bytes to fill the upper and lower registers associated with right/left channel delay. The decimal value of D0-D13 equals the number of samples to delay. The maximum number of delayed samples is 8191 for the TPA5050. This equates to 170.65 ms [8191 x (1/fs)] at 48 kHz. Table 4. Audio Delay Registers (0x02-0x05) (1)
D13 0 0 1 (1) D12 0 0 1 D11-D2 0 0 1 D1 0 0 1 D0 0 1 1 FUNCTION Left and Right audio is passed to output with no delay. Left and Right audio is delayed by 1 sample (1/fs = delay time) Left and Right audio is delayed by 8191 samples (8191/fs = delay time)
Default values are in bold.
FRAME DELAY REGISTERS (0x06)
This register can be used to specify delay in video frames instead of audio samples. When the MSB is set to 1, the audio delay registers (0x01-0x04) are bypassed and the Frame Delay Register is used to set the delay based on the frame rate (D6), audio sample rate (D5-D3), and number of frames to delay (D2-D0). The total audio delay time is calculated by the following formula: Audio Delay (in samples) = int [# Delay Frames x (1/Frame Rate) x Audio Sample Rate]
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If the result of the formula above is greater than the maximum number of delay samples (8191 for TPA5050), then the value is limited to this maximum before passing to the delay block. Table 5. Frame Delay Registers (0x06) (1)
D7 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 (1) Default values are in bold. 0 0 1 0 1 1 D6 D5 D4 D3 D2 D1 D0 FUNCTION Settings in this register are masked and audio delay is determined by settings in the right/left audio delay registers. Right/left audio delay registers are masked and delay is determined by settings in this register. Frame rate = 50 Hz Frame rate = 59.94 Hz Audio sample rate = 32 kHz Audio sample rate = 44.1 kHz Audio sample rate = 48 kHz Audio sample rate = 88.2 kHz Audio sample rate = 96 kHz Audio sample rate = 176.4 kHz Audio sample rate = 192 kHz Audio sample rate = 192 kHz Delay frames = 1 Delay frames = 2 Delay frames = 8
RJ PACKET LENGTH REGISTERS (0x07)
This register is only used in right justified mode. The decimal value of bits [5:0] represents the width of the useable data in a right justified audio stream. The number of BCLK transitions between LRCLK transitions must be greater than or equal to the packet length selected in this register. The maximum packet length value is 24 bits. Any setting greater whose numerical value is greater than 24 bits is limited to the maximum 24 bits. Table 6. RJ Package Length (0x07) (1)
D5 0 0 0 (1) D4 0 0 1 D3 0 0 1 D2 0 0 X D1 0 0 X D0 0 1 X Packet length = 0 bits Packet length = 1 bits Packet length = 24 bits FUNCTION
Default values are in bold.
COMPLETE UPDATE REGISTER (0x08)
Since the audio delay values are divided among several registers, it is likely that multiple writes would be necessary to configure the device. This may cause interruptions in the audio stream and unwanted pops and clicks might occur as register data is passed to delay functional block. To avoid this from happening, the Complete Update register is used to transfer the user settings from the register file to the delay functional block when a 1 is written to the LSB. For example, if the right delay is set to 35 samples, and the left delay is set to 300 samples, the device holds the right channel in MUTE until 35 samples of audio data have passed, and holds the left channel in MUTE until 300 samples of audio data have passed. Note that the individual channels can be muted using the upper bits of the Control Registers without writing to the Complete Update registers.
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Table 7. Complete Update Registers (0x08) (1)
D7-D1 X X (1) D0 0 1 FUNCTION No data from the register settings is passed to the delay block. Stream type, right/left delay or frame delay, and packet length is passed to the delay functional block.
Default values are in bold.
APPLICATION EXAMPLES
The following are some examples of I2C commands used to read or write to the TPA5050. For all conditions, assume the address of the TPA5050 is set to 001. Single Byte Write In this example, the TPA5050 is set to mute both left and right channels, and to operate in I2S mode.
Start D2 ACK 01 ACK C0 ACK Stop
TPA5050 Address and Write
Register Address
Data
Multiple Byte Write In this example, the TPA5050 is set to make both the left and right channels active, operate in I2S mode, delay the right channel by 4095 samples, and delay the left channel by 4096 samples. This is a sequential write, so all registers must have data written to them.
Start D2 ACK 01 ACK 00 ACK 0F ACK FF ACK
TPA5050 Address and Write 10 ACK
Register Address (Control Register) 00 ACK
Data (Control Register) 00
Data (Right Delay Upper Bits) ACK 00 ACK
Data (Right Delay Lower Bits) 01 ACK
Data (Left Delay Upper Bits)
Data (Left Delay Lower Bits)
Data (Frame Delay)
Data (RJ Packet = 0Bits)
Data (Complete Update)
Stop
Combination Single Byte Write and Sequential Write In this example, the TPA5050 is set to operate in the Right Justified mode, with a packet length of 16 bits. The device is to delay the audio signal by 40 ms using the Frame Delay function. Assume the audio sample rate (fs) = 48 kHz, and the Frame rate = 50 Hz. This is a combination of single writes and a sequential write. Since the Right Justified mode is set in the Control Register, and the Frame Delay is set in register 0x06, the data in registers 0x02-0x05 can be ignored.
Start D2 ACK 01 ACK 01 ACK Stop
TPA5050 Address and Write Start D2 ACK
Register Address (Control Register) 06 ACK
Data (Control Register) 91 ACK 10 ACK 01 ACK Stop
TPA5050 Address and Write
Register Address (Frame Delay)
Data (Frame Delay)
Data (RJ Packet = 16 Bits)
Data (Complete Update)
Note that in every circumstance where a delay was written into the memory of the TPA5050, a 1 must be written to the Complete Data register for the change to take effect. This does not apply to muting, which occurs in the Control register.
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Single Byte Read In this example, one byte of data is read from the Control Register (0x01). After the data (represented xx) by is read by the master device, the master device issues a Not Acknowledge, before stopping the communication.
Start D2 ACK 01 ACK Start D3 ACK XX No ACK Stop
TPA5050 Address and Write
Register Address (Control Register)
TPA5050 Address and Read
Data Read (Control Register)
Multiple Byte Read Often, when it is necessary to read what is contained in one register, it is necessary to determine what information is contained in all registers. In such a case, a sequential read should be used. In situations where data must be read from a register at the beginning (0x01), and a register towards the end (0x07), a sequential read is likely to be faster to implement than multiple single byte reads. In this example, a sequential read is initiated with the Control Register (0x01), and ends with the Complete Update Register (0x08).
Start D2 ACK 01 ACK Start D3 ACK XX ACK XX ACK
TPA5050 Address and Write
Register Address (Control Register)
TPA5050 Address and Read
Data Read (Control Register)
Data Read (Right Delay Upper)
XX
ACK
XX
ACK
XX
ACK
XX
ACK
XX
ACK
Data Read (Right Delay Lower) XX No ACK
Data Read (Left Delay Upper) Stop
Data Read (Left Delay Lower)
Data Read (Frame Delay)
Data Read (RJ Packet Length)
Data Read (Complete Update)
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DEVICE CURRENT CONSUMPTION The TPA5050 draws different amounts of supply current depending upon the conditions under which it is operated. As VDD increases, so too does IDD. Likewise, as VDD decreases, IDD decreases. The same is true of the sampling frequency, fs. An increase in fs causes an increase in IDD. Figure 11 illustrates the relationship between operating condition and typical supply current.
SUPPLY CURRENT vs SAMPLING FREQUENCY
5 4.5 BCLK = 64 fs Data = 24 bit VDD = 3.6 V
IDD - Supply Current - mA
4 3.5 3 2.5
VDD = 3.3 V 2 1.5 1 0.5 0 32 52 72 92 112 132 152 172 192 VDD = 3 V
fs - Sampling Frequency - kHz
Figure 11. Typical Supply Current
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device TPA5050RSAR TPA5050RSARG4 TPA5050RSAT TPA5050RSATG4
(1)
Status (1) ACTIVE ACTIVE ACTIVE ACTIVE
Package Type QFN QFN QFN QFN
Package Drawing RSA RSA RSA RSA
Pins Package Eco Plan (2) Qty 16 16 16 16 3000 Green (RoHS & no Sb/Br) 3000 250 250 TBD Green (RoHS & no Sb/Br) TBD
Lead/Ball Finish CU NIPDAU Call TI CU NIPDAU Call TI
MSL Peak Temp (3) Level-2-260C-1 YEAR Call TI Level-2-260C-1 YEAR Call TI
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2006, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Low Power Wireless www.ti.com/lpw

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